1. Field of the Invention
The present invention relates to electronic packages and fabrication methods thereof, and more particularly, to an electronic package having wafer-level circuits and a fabrication method thereof.
2. Description of Related Art
Along with the rapid development of electronic industries, electronic products are developed toward the trend of multi-function and high performance. Current chip packaging technologies have developed various types of flip-chip packaging modules such as chip scale packages (CSPs), direct chip attached (DCA) packages and multi-chip module (MCM) packages.
FIGS. 1A to 1F are schematic cross-sectional views showing a method for fabricating a semiconductor package 1 according to the prior art.
Referring to FIG. 1A, a semiconductor structure is provided. The semiconductor structure has a silicon substrate 10, a circuit portion 11 formed on the silicon substrate 10, a plurality of semiconductor chips 12 flip-chip bonded to the circuit portion 10, and an underfill 13 formed between the circuit portion 11 and the semiconductor chips 12.
Referring to FIG. 1B, an encapsulant 14 is formed on the circuit portion 11 to encapsulate the semiconductor chips 12 and the underfill 13.
Referring to FIG. 1C, an upper portion of the encapsulant 14 is removed to expose the semiconductor chips 12.
Referring to FIG. 1D, a support member 15 is disposed on the encapsulant 14 and the semiconductor chips 12. The support member 15 has an adhesive layer 150, a silicon plate 151 and an insulating layer 152 sequentially stacked on one another. The insulating layer 152 is made of a dielectric material and formed through a chemical vapor deposition (CVD) process.
Referring to FIG. 1E, the silicon substrate 10 is removed to expose a lower surface of the circuit portion 11. Then, an insulating layer 17 is formed on the lower surface of the circuit portion 11. The circuit portion 11 is partially exposed from the insulating layer 17 for mounting solder balls 18.
Referring to FIG. 1F, a singulation process is performed along cutting paths S of FIG. 1E to obtain a plurality of semiconductor packages 1. The silicon plate 151 facilitates to enhance the rigidity of the semiconductor packages 1 and improve the heat dissipating effect of the semiconductor chips 12.
However, since a molding process is required to form the encapsulant 14 and a grinding process is required to remove the upper portion of the encapsulant 14, the overall fabrication process is quite complicated, labor and time consuming and needs various equipment, thereby incurring a high fabrication cost.
Further, a large CTE (Coefficient of Thermal Expansion) mismatch between the semiconductor chips 12 and the encapsulant 14 easily causes warping of the overall structure before singulation.
Furthermore, since the encapsulant 14 easily absorbs moisture, it can also result in warping of the overall structure before singulation.
As a result of warping, the semiconductor chips 12 easily crack and the solder balls 18 easily delaminate from the circuit portion 11, thus reducing the product reliability.
Therefore, how to overcome the above-described drawbacks has become critical.